Information processing apparatus

ABSTRACT

A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation application under 37 CFR §1.53(b) ofapplication Ser. No. 11/046,453, filed on Jan. 28, 2005, which claimspriority from Japanese Patent Application Serial No. 2004-021207, filedon Jan. 29, 2004, the content of which is hereby incorporated byreference into this application.

FIELD OF THE INVENTION

The present invention relates to an information processing apparatuscomprising a CPU, a memory and a prefetch means. It particularly relatesto an interruption routine thereof and a technique prefetching a targetinstruction of RTE (return from exception). Further it relates to atechnique effectively applicable to prefetching a target instruction forbranch to a subroutine and to storing a target instruction of RTS(return from subroutine).

BACKGROUND OF THE INVENTION

Recently, while the operating frequency of CPUs has remarkably increasedthan before, the increase of operating frequency of memories has gentlyincreased compared with that of CPUs to meet the requirement for greatercapacities. The resultant disparity between CPUs and memories inoperating frequency is bringing to a problem of no significantimprovement in the overall performance of systems.

A prefetch buffer or cache readable with high speed is generally used tosolve the problem as follows. Instructions to be necessary in advanceare stored in the prefetch buffer or cache, and they are read from that.Accordingly, the delays in reading out of the memory are covered withthe function of the prefetch buffer or cache, and devices with thememory are improved.

When the program being executed includes any branch instruction, it isnecessary to execute a prefetch that properly anticipates a target(destination) instruction for branch and reads it out to a prefetchbuffer or the like.

One of Methods of the prefetch is that anticipates the target addressfor branch on the basis of history of the execution of the branchinstruction and reads the target address anticipated branchingdestination instruction out of the memory into the prefetch buffer.However, this involves another problem that, where processing isactually branched in accordance with a branch instruction, aconfiguration in which the aforementioned anticipation is done when theinstruction is executed, the series of instructions after the branchingcannot be prefetched in time.

In view of this problem, a technique by which the possibility of branchis anticipated at the stage of prefetching instructions and prefetchingthe subsequent series of instructions is disclosed in Japanese PatentLaid-Open No. H6 (1994)-274341 (hereafter “Patent Reference 1”).

SUMMARY OF THE INVENTION

According to the technique disclosed in Patent Reference 1 cited above,only the target instruction for branch is prefetched, but neither abranch to an interruption routine nor to a return from an interruption(execution) routine to a main routine is.

For this reason, in an application involving many interruptions, therestill remains the problem of no improvement in performance. Or in anapplication needing a high level of real time performance, there arisesa problem that no sufficient time for interruptions can be secured.

A first object of the present invention is to provide an informationprocessing technique permitting effective prefetching, ensuring highperformance and meeting a high-level requirement for real timeperformance even with an application involving many interruptions.

Furthermore, according to the technique disclosed in Patent Reference 1cited above, the accuracy of prefetcing the target instructions forbranch is dependent on the capacity of a branch history table, andtherefore involves a problem of a higher system price because enhancingits performance would require a high-speed and large-capacity RAM forthe branch history table.

A second object of the present invention is to provide ahigh-performance information processing technique permitting at low costupdating of an instruction buffer ready for effective prefetching branchinstructions and returning from the subroutine with a small volume ofhardware.

The above-described and other objects and novel features of the presentinvention will become apparent from the following description in thisspecification when taken in conjunction with the accompanying drawings.

Typical aspects of the invention disclosed in the present applicationwill be briefly described below.

In order to achieve the first object of the invention stated above, theinvention is applied to an information processing apparatus which isprovided with a CPU, a memory and a prefetch means which prefetches aseries of instructions comprising a predetermined number of instructionsand data before the CPU executes any of the instructions or data in theseries of instructions, and is characterized as follows.

The information processing apparatus is further provided with a prefetchaddress calculation means which, when an interruption request arises,prefetches an interruption vector table, further extracts the head(first) address of an interruption routine out of read data in theinterruption vector table prefetched, and thereby prefetches the headaddress of the interruption routine.

The information processing apparatus is further provided with prefetchaddress generating means which, at the time when the series ofinstructions is stored into a prefetch buffer, detects a prescribed“return from interruption as exception (RTE)” instruction or “returnfrom subroutine (RTS)” instruction contained in the series ofinstructions and prefetches target instructions of RTE and RTS.

In order to achieve the second object of the invention stated above, theinvention is applied to an information processing apparatus which isprovided with a CPU, a memory and a prefetch means which prefetches aseries of instructions including a predetermined number of instructionsand data before the CPU executes any of the instructions or data in theseries of instructions, and is characterized as follows.

The information processing apparatus is further provided with a prefetchaddress calculation means which prefetches a branch target address bydecoding at least one information for calculation of branch targetaddress and a series of instructions for branch including branchinstructions, from a current instruction buffer storing the series ofinstructions currently accessed with the CPU.

The information processing apparatus is further provided with a prefetchaddress calculation means which prefetchs a branch target address bydecoding at least one information for calculation of branch targetaddress and a series of instructions for branch including branchinstructions, from a current instruction buffer storing a series ofinstructions currently accessed with the CPU and a previous instructionbuffer storing a series of instructions previously accessed with theCPU.

The information processing apparatus is further provided with at leastone RTS buffer for storing a series of target instructions of RTS, and acurrent instruction buffer for storing a series of instructionscurrently accessed by the CPU. The series of instructions in the currentinstruction buffer are stored into the RTS buffer.

Advantages achieved by some of the most typical aspects of the inventiondisclosed in the present application will be briefly described below.

By prefetching interruption vectors and an interruption routine, thespeed of branching into the interruption routine can be increased.

By detecting a return from interruption (RTE) instruction andprefetching the target instruction (destination) of RTE before the CPUexecutes the instruction, the speed of return from the interruptionroutine can be increased.

By detecting a return from subroutine (RTS) instruction and prefetchingthe target address of RTS before the CPU executes the instruction, thespeed of return from the subroutine can be increased.

When the series of instructions for branch is to be decoded from thecurrent instruction buffer and the target address for branch is to beprefetched, by decoding only series of instructions for branchsatisfying specific conditions, branch instructions can be effectivelyprefetched with only a small volume of hardware.

Since the RTS instruction buffer for storing the series of instructionsregarding the target addresses of RTS instructions is updated with aseries of instructions from the current instruction buffer, it ispossible to reduce performance deteriorations due to contention inmemory accessing for the updating of the cache or buffers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an overall configuration of an information processingapparatus, which is Embodiment 1 of the present invention.

FIG. 2 is a timing chart of the actions of the CPU in the informationprocessing apparatus of Embodiment 1 of the invention.

FIG. 3 illustrates the relationships among addresses, bits and entriesin a case in which a program is stored into a memory in the informationprocessing apparatus of Embodiment 1 of the invention.

FIG. 4 is a timing chart of the actions of the memory in the informationprocessing apparatus of Embodiment 1 of the invention.

FIG. 5 is a timing chart showing a case in which a program is executedin a configuration having a memory with an access latency 2 and onlyconsecutive instructions are prefetched in a cache in the informationprocessing apparatus of Embodiment 1 of the invention.

FIG. 6 shows a detailed configuration of a prefetch address calculationunit in the information processing apparatus of Embodiment 1 of theinvention.

FIG. 7 illustrates the state transition of the prefetch request statemachine in the information processing apparatus of Embodiment 1 of theinvention.

FIG. 8 illustrates outputs pfreq and pftype matching the states shown inFIG. 7 in the information processing apparatus of Embodiment 1 of theinvention.

FIG. 9 shows a detailed configuration of an address calculation unit inthe information processing apparatus of Embodiment 1 of the invention.

FIG. 10 is a timing chart of the actions of the information processingapparatus of Embodiment 1.

FIG. 11 shows an overall configuration of an information processingapparatus, which is Embodiment 2 of the invention.

FIG. 12 shows a detailed configuration of a instruction buffer in theinformation processing apparatus of Embodiment 2 of the invention.

FIG. 13 shows a detailed configuration of a RTS instruction buffer inthe information processing apparatus of Embodiment 2 of the invention.

FIG. 14 shows a detailed configuration of a prefetch address calculationunit in the information processing apparatus of Embodiment 2 of theinvention.

FIG. 15 illustrates a branching series of instructions consisting ofthree instructions, No. 1 through No. 3, supposed for the informationprocessing apparatus of Embodiment 2 of the invention.

FIG. 16 is a timing chart of the actions of the information processingapparatus of Embodiment 2 of the invention.

FIG. 17 illustrates an example of program arrangement on the memory inthe information processing apparatus of Embodiment 2 of the invention.

FIG. 18 is a timing chart of the actions of prefetch address calculationunit in the information processing apparatus of Embodiment 2 of theinvention in a case in which there is a valid series of instructions forbranch spanning two entries.

FIG. 19 illustrates an example of program arrangement in the informationprocessing apparatus of Embodiment 2 of the invention in a case in whichthere is a valid series of instructions for branch spanning entry 8 andentry 9.

FIG. 20 illustrates an example of program flow in the informationprocessing apparatus of Embodiment 2 of the invention.

FIG. 21 is a timing chart of the actions to update the RTS instructionbuffer in the program flow illustrated in FIG. 20 in the informationprocessing apparatus of Embodiment 2 of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described indetail below with reference to the accompanying drawings. In all thedrawings illustrating the preferred embodiments of the invention,members having the same functions will be denoted by respectively thesame signs in principle, and their description will not be repeated.

Embodiment 1

Embodiment 1 of the invention will be described with reference to FIG. 1through FIG. 10.

FIG. 1 shows an overall configuration of an information processingapparatus, which is Embodiment 1 of the present invention.

The information processing apparatus of this embodiment comprises a CPU(1), a prefetch address calculation unit (2), a control unit (3), amemory (4), a cache (5), a selector 0 (6), a data buffer (7), aninstruction buffer (8), an interruption controller (hereafter “INTC”)(9) and a selector 1 (10). In this configuration, the prefetch addresscalculation unit (2) is provided as a prefetch address calculationmeans. The control unit (3), the selector 0 (6), the data buffer (7),the instruction buffer (8), and the selector 1 (10), including thisprefetch address unit (2), are provided to constitute a prefetch means.

The memory (4) stores programs, receives a memory address signal memadr[31:4] through a signal line 22 and a memory read signal memareadthrough a signal line 23, and outputs a memory read data signal memrd[127:0] through a signal line 21.

Expression memadr [31:4] here collectively refers to 28-bit signalsconsisting of memadr [31], memadr [30], . . . , memadr [4]. In the restof the description of this embodiment, the same applies to other signalsas well.

Incidentally in this embodiment, the access latency and the read widthof the memory is supposed to be 2 and 128 bits, respectively.

The CPU (1) reads necessary instruction codes out of the memory (4) andexecutes programs. Though not shown, it is provided with a calculationunit and an operation control unit. The calculation unit includes anALU(an arithmetic and logic calculation unit) for executing necessaryarithmetic and logic calculation to data stored in the memory orelsewhere, a program counter, an accumulator, a general register and thelike. The operation control unit generates operation control signals forthe calculation unit by decoding inputted instructions.

The CPU (1) outputs through a signal line 14 a CPU address signal cpuadr[31:0] indicating an instruction code and an address of data which theCPU (1) is to access.

The CPU (1) further outputs a head address signal vbr [31:0] of a vectortable through a signal line 11, a stored program counter signal spc[31:0] through a signal line 12 and a signal spcupdt indicating thevalid timing of spc [31:0] through a signal line 13, to use incalculating by prefetch address calculation unit (2).

A CPU read data signal cpurd [31:0], which is a data read value of aninstruction or data at an address indicated by cpuadr [31:0], isinputted to the CPU (1) from the selector 1 (10) through a signal line15.

When cpurd [31:0] does not become definite, CPU wait signal cpuwait forstopping accessing of the CPU is inputted to the CPU (1) from thecontrol unit (3) through a signal line 35.

An interruption request signal intreq and an interruption vector signalintvec [3:0] are also inputted to the CPU (1) from the INTC (9) througha signal line 32 and a signal line 33, respectively, and outputs aninterruption accept signal intack to the INTC (9) through a signal line36.

Incidentally in this embodiment, the instruction width of the CPU (1) issupposed to be 16 bits, and the data width and address space, to be 32bits, respectively.

The Prefetch address calculation unit (2), when a series of instructionsis stored into the instruction buffer (8), detects a RTE (return fromexception(interruption)) instruction from the stored series ofinstructions before the RTE instruction is executed. The unit (2)calculates an address to be accessed next according to the RTEinstruction, and generates a request for reading out of the memory (4) aseries of instructions which includes an instruction of the address.

An interruption request signal intreq and an interruption vector signalintvec [3:0] are further inputted from the INTC (9) to the prefetchaddress calculation unit (2) through the signal line 32 and the signalline 33, respectively. And an interruption acknowledgement signal intackis also inputted to the unit (2) from the CPU (1) through the signalline 36. The Prefetch address calculation unit (2) calculates a targetaddress of those signals before the CPU (1) reads an interruption vectortable and an interruption routine, and it generates a request forreading out of the memory (4) a series of instructions which includesthe target address.

For the aforementioned prefetch, the prefetch address calculation unit(2) outputs a prefetch address signal pfadr [31:0] indicating theaddress of the prefetch instruction to the control unit (3) through asignal line 30, and outputs a prefetch request signal pfreq indicatingthe generation of a prefetch request to the unit (3) trough a signalline 29.

The prefetch address calculation unit (2) further receives the followingseveral signals through the respective signal lines, namely, vbr [31:0],spc [31:0] and spcupdt from the CPU (1) through their respective signallines (11),(12) and (13), an instruction buffer output signal ibuf[127:0] from the instruction buffer (8) through a signal line 18, a databuffer output signal dbuf [127:0] from the data buffer (7) through asignal line 19, a signal pfack from the control unit (3) through asignal line 31, and a prefetch update signal dbupdt indicating the inputtiming of dbuf [127:0] from the control unit (3) through a signal line27. The prefetch address calculation unit uses them for the calculationof pfadr [31:0] and pfreq.

The cache (5) stores the following instructions, namely, instructionswhich have been once executed or data once referenced, and instructionsor data whose prefetch are requested by the prefetch address calculationunit. The Cache (5) can read with high speed any of the instructions ordata stored therein.

Reading any instruction out of the cache (5) is executed by inputtingfrom the control unit (3) a cache read address signal cacheadr [31:4]through a signal line 24 and a cache read signal cacheread through asignal line 25. When an instruction of the address indicated by cacheadr[31:4] is stored, the cashe (5) asserts a cache hit signal cachehitthrough a signal line 26, and outputs an instruction stored at the sametime as a cache read data cacherd [127:0] through a signal line 20.

Actually, control signals for updating instructions or data stored inthe cache are inputted to the cache from the control unit (3), butdetails are skipped in FIG. 1, and their updating are supposed to bedone at the same time as reading the instructions or data out of thememory (4).

The instruction buffer (8) holds a series of instructions including aninstruction currently being executed, and outputs it as an instructionbuffer output signal ibuf [127:0] through signal line 18.

The instruction buffer (8) receives through a signal line 28 aninstruction buffer update signal ibupdt which indicates the updatetiming of values held by the instruction buffer, and captures the signalof cacherd [127:0].

The data buffer (7) holds the vector table whose prefetch is requestedby prefetch address calculation unit (2), and outputs it as a databuffer output signal dbuf [127:0] through a signal line 19. The databuffer (7) receives through a signal line 27 a data buffer update signaldbupdt indicating the update timing of values held by the data buffer,and captures the signal of memrd [127:0] from the memory (4).

The selector 0 (6) receives a selection signal sel0 [1:0] from thecontrol unit (3) through a signal line 17, selects one signal out ofdbuf [127:0], cacherd [127:0] and memrd [127:0], and outputs the resultof selection as selrd [127:0] through a signal line 34. The value ofsel0 [1:0] and the selected signal are 2:dbuf [127:0], 1:cacherd [127:0]and 0:memrd [127:0].

The selector 1 (10) receives a selection signal sell [1:0] from thecontrol unit (3) through a signal line 16, selects 32 bits from selrd[127:0], and outputs the result of selection as cpurd [31:0]. The valueof sell [3:0] and the selected signal are 0:selrd [127:96], 1:selrd[95:64], 2:selrd [63:32] and 3:selrd [31:0].

The above-described selection signals sel0 [1:0] and sel0 [1:0] for theselector 0 (6) and the selector 1 (10), respectively, select an outputsignal by which the control unit (3) can earliest supply instructions ordata corresponding to the access from the CPU (1).

The INTC (9) outputs the interruption request signal intreq and theinterruption vector signal intvec [3:0], and requests branch to aninterruption routine corresponding to the interruption vector of the CPU(1).

The INTC (9) keeps on outputting intreq and intvec [3:0] until theinterruption accept signal intack indicating acceptance of theinterruption is inputted from the CPU (1).

The control unit (3) performs control pertaining to transfers ofinstructions and data between the CPU (1) and the memory (4) byinputting/outputting control signals to and from the CPU (1), theprefetch address calculation unit (2), the memory (4), the cache (5),the selector 0 (6), the data buffer (7), the instruction buffer (8) andthe selector 1 (10).

More specifically, as will be described later, the control unit (3)controls processing in those sections by asserting the necessary ones ofvarious control signals which are inputted at prescribed timings.

Next, details of the elements of the configuration will be described.Before describing the details, the actions of the CPU (1) supposed inthis embodiment and the arrangement in a case in which the programs tobe executed by the CPU (1) are stored in the memory will be described.

FIG. 2 is a timing chart of the actions of the CPU (1).

The upper part of FIG. 2 shows an example of a series of instructions tobe executed by the CPU (1) and actions of the pipeline performed by theCPU (1) at the time of processing the series of instructions.

The CPU (1) processes one instruction in a five-stage pipelinecomprising an instruction fetch (IF) stage of reading the instructionfrom the memory (4), instruction decoding (ID) stage of decoding theinstruction, an execution (EX) stage of executing the instruction, amemory access (MA) stage of reading data out of the memory (4), and awrite-back (WB) stage of writing into the memory (4).

Incidentally, accesses to the memory (4) occur at the IF stage, the MAstage and the WB stage of each instruction. While the IF stage, the IDstage and the EX stage are executed in every case, there are cases thatthe MA stage and the WB stage are not executed depending on theinstruction. Further, since two 16-bit instructions are read at the sametime on a bus of a 32-bit width, the IF stage is not executed in one ofevery two instructions. In FIG. 2, unexecuted instruction stages arewritten in small letters.

The lower part of FIG. 2 shows the waveforms of input/output signals ofthe CPU (1) generated corresponding to the pipeline actions shown in theupper part of FIG. 2.

In FIG. 2, cycle 0 is the IF stage of instruction 64 at address 128. Incycle 0, address 128 is outputted from the CPU (1) to cpuadr, and anaccess to an instruction in address 128 is generated.

Then for the next cycle 1, there is shown a situation in which any datato be accessed in cycle 1 is not definite on account of a delay inoutputting from the memory or some other reason. At this time, thecontrol unit (3) asserts cpuwait, and instructs the CPU (1) to suspendinstruction processing.

The data is made definite in the next cycle 2 and, in response to thenegation of cpuwait, the CPU (1) resumes processing. In cycle 2, aninstruction at address 128 for the access in cycle 0 is inputted fromcpurd to the CPU (1).

Incidentally in FIG. 2, the address output of address 128 and theinstruction and data read out in response to the access are expressed as“a128”.

In cycle 3, the INTC (9) outputs interruption factor (vector) 2 as theinterruption request signal intreq and the interrupt factor signalintvec [3:0], requests branch to an interruption routine correspondingto the interruption vector 2 of the CPU (1).

In cycle 4, the CPU (1) informs the INTC (9) the acceptance ofinterruption according to the interruption vector 2 by asserting intack,and in the next cycle 5 starts processing the branch of the interruptionvector 2 into the interrupt routine.

In cycle 5, The CPU (1), in order to store the target (destination)address of returning from the interruption routine in a memory elementsuch as a built-in RAM, outputs the target address 130 as spc [31:0] andasserts a signal spcupdt indicating the effective timing of spc [31:0].In the overall configuration diagram of FIG. 1, illustration of theconnection to the memory element, such as a built-in RAM, spc [31:0] andspcupdt is omitted.

In cycle 6, the CPU (1) reads in the interruption vector table out ofthe memory.

The interruption vector table here is a table which stores the headaddresses (interruption vectors) of the interruption routinecorresponding to interruption factors, in which the addresses, beginningwith an address indicated by vbr [31:0], are arranged in series frominterruption vector 0 onward. In this embodiment, vbr [31:0] is set to0, and the address of the interruption vector is in series of 0, 4, 8, .. . beginning with interruption vector 0.

In order to read the accepted interruption vector of interruption factor2 out of the memory, address 8 is accessed.

In cycle 7, the interruption vector of interruption factor 2 is readout. In this embodiment, the interruption vector as interruption factor2 is supposed to be equal to 512.

In cycle 8, accessing the head address 512 of the interruption routineof interruption factor (vector) 2 is started.

Cycle n is the IF stage of a return instruction RTE from theinterruption (exception) routine. Through the ID and EX stages of RTE,the target address 132 of RTE instruction stored in the memory elementsuch as a built-in RAM, is read in cycles n+3 and n+4. In FIG. 1,illustration of the signal for the CPU (1) to read the stored targetaddress of RTE is omitted.

In cycle n+5, the instruction concerning the target address of RTE isaccessed, hereafter the processing of instructions by the main routineis executed.

FIG. 3 illustrates the relationships among addresses, bits and entriesin a case in which a program is stored into the memory (4).

As shown in FIG. 3, the instructions and data constituting the programare sequentially arranged in the ascending order of address number inthe descending order of bits, with eight instructions (or data)constituting one entry. Hereinafter, instructions or data constitutingone entry will be referred to as a series of instructions.

In this embodiment, the memory (4) is accessed on an entry-by-entrybasis. For example, addresses 0, 2, 4, 6, 8, 10, 12 and 14 are accessedat the same time as an access to entry 0. Further, each of entry 0,entry 8, entry 32 and entry 50 shown in FIG. 3 stores the vaninstruction and the RTE instruction of the interruption routinecorresponding to the interruption vector, the main routine and theinterruption factor 2.

Where instructions or data of a 16-bit width are to be stored in such amemory (4), the bits of the address have differentiating roles as statedbelow.

Bits 15 through 4: For entries

Bits 3 through 1: For positions of instructions or data in the sameentry

Bits 0: For the upper 8 bits and lower 8 bits in instructions or data

Next, the actions of the memory (4) will be described. FIG. 4 is atiming chart of the actions of the memory (4).

In cycle 0, the control unit (3) outputs entry 0 as memadr, and gives arequest to read entry 0 to the memory (4) by asserting memaread. In FIG.4, the address output of entry 0 and instructions and data read out inresponse to the access are expressed as “e0”.

In this embodiment, since the access latency of the memory is set to twocycles, data pertaining to this access is made definite in cycle 2, andhereupon the memory (4) outputs instructions or data as memard.

A timing chart, showing a case in which a program is executed in aconfiguration having the memory (4) with this access latency 2 and onlya series of instructions are prefetched to a cache, is given as FIG. 5.

The instructions to be executed, the timing of interruption requestingand the interruption vector are the same as those respectively describedabove with reference to FIG. 2.

As show in FIG. 5, cache errors occur in accessing the interruptionvector (cycle 6), accessing the van instruction of the interrupt routine(cycle 10), and accessing the van instruction on the target instructionof RTE (cycle n+5), where accessing by the CPU becomes non-series, andprocessing by the CPU is suspended until the instructions or data to beaccessed become definite, inviting a deterioration in performance.

Next, details of the prefetch address calculation unit (2) will bedescribed. FIG. 6 shows a detailed configuration of the prefetch addresscalculation unit (2).

The Prefetch address calculation unit (2) is provided with eightinstruction type pre-decoders, including an instruction pre-decoder 0(210), an instruction pre-decoder 1 (211), . . . , and an instructionpre-decoder 7 (217) for decoding to find out whether or not inputtedinstructions are RTE instructions, an OR gate (203), a prefetch requeststate machine (201) and an address calculation unit (202).

Each of the 16-bit segments into which ibuf [127:0] is divided, isinputted to each of the instruction pre-decoder 0 (210), the instructionpre-decoder 1 (211), . . . , and the instruction pre-decoder 7 (217).

For instance, the instruction of the head address in the series ofinstructions of the entry outputted by ibuf [127:0] is inputted to theinstruction pre-decoder 0 (210). When the inputted instruction is an RTEinstruction, the instruction pre-decoder 0 (210) asserts a signal rtn0,which indicates that the instruction decoded onto the signal line 220 isan RTE instruction.

Similarly, the instruction pre-decoder 1 (211) decodes the secondinstruction in the series of instructions of the entry outputted by ibuf[127:0], and outputs the result as a signal rtn1 onto a signal line 221.

The types of the third, fourth, . . . , sixth instructions or data arealso decoded. Similarly, the instruction pre-decoder 7 (217) decodes theeighth instruction in the series of instructions of the entry outputtedby ibuf [127:0], and outputs the result as a signal rtn7 onto a signalline 227.

The “or” of rtn0, rtn0, rtn7 is calculated by the OR gate (203), andoutputted as a signal rtn onto a signal line 204. According to theabove-mentioned configuration, when there is at least one RTEinstruction in the series of instructions of the entry outputted by ibuf[127:0], rtn is asserted.

The rtn (204), dbupdt (27), pfack (31) and intreq (32) are inputted asconditions of state transition of the prefetch request state machine(201). Further, the prefetch request state machine (201) decodes thecurrent state, and outputs the result as pfreq (29) and pftype (205).

States, conditions of inter-state transition and outputs correspondingto different states will be described in detail afterwards withreference to FIG. 7 and FIG. 8.

The address calculation unit (202) takes in pftype (205), dbuf [127:0](19), intvec [8:0] (33), vbr [31:0] (11), spc [31:0] (12), spcupdt (13)and intack (36),and then calculates an address to be prefetched. Thecalculated address is outputted through the signal line 30 as prefetchaddress signal pfadr [31:0] indicating the target address of theprefetch instruction. Details of the address calculation unit (202) willbe described afterwards with reference to FIG. 9.

FIG. 7 illustrates the state transition of the prefetch request statemachine (201).

The prefetch request state machine (201) has six states including anIDLE state in which no request is made, a VECF0 state in which aninterruption vector is prefetched, a VECF1 state, a JMP0 state in whichthe head address of interruption routine is prefetched, a JMP1 state andan RIN state in which a target address of return from interruption isprefetched. The initial state is the IDLE state.

The IDLE state is made transition to the same state when intreq is 0, tothe VECF0 state when intreq is 1, and to the RIN state when rtn is 1,respectively.

The VECF0 state is made transition to the same state when pfack is 0 andto the VECF1 state when pfack is 1.

The VECF1 state is made transition to the same state when dbupdt is 0and to the JMP0 state when dbupdt is 1.

The JMP0 state is made transition to the JMP1 state unconditionally.

The JMP1 state is made transition to the same state when pfack is 0 andto the IDLE state when pfack is 1.

The RIN state is made transition to the same state when pfack is 0 andto the IDLE state when pfack is 1.

FIG. 8 illustrates outputs pfreq (29) and pftype (205) corresponding tothe states shown in FIG. 7. As illustrated, in the VECF0 state, the JMP1state and the RTN state, the prefetch request pfreq is asserted to thecontrol unit (3) and the prefetch type pftype is outputted to theaddress calculation unit (202). The meanings of pftype here are definedas follows:

0: No prefetch

1: Request of prefetching the interruption vector

2: Request of prefetching the van instruction of the interruptionroutine

3: Request of prefetching the target address of return from theinterruption (RTE) instruction

FIG. 9 shows a detailed configuration of the address calculation unit(202). The address calculation unit (202) comprises an INTVEC holdingregister (412), a two-bit left shifter (401), an adder (402), a selector0 (403), a stored PC holding register (404) and a selector 1 (405).

The INTVEC holding register (412) captures the value of intvec [3:0](33) by asserting intack (36), and outputs the value it holds as asignal intvec 1 [3:0] (413) through a signal line 413.

The two-bit left shifter (401) shifts intvec 1 [3:0] (413) leftward bytwo bits, performs a calculation to add two lowest-order bits 0, i.e. toquadruple the input, and outputs the result as a vector offset signalvecofst [5:0] through a signal line 405.

The adder (402) adds vbr [31:0] (11) and vecofst [5:0] (405), andoutputs the result as a vector address signal vecadr [31:0] through asignal line 411.

The selector 0 (403), to which two lower-order bits intvec 1 [1:0] ofintvec 1 [3:0] (413) is inputted as a selection signal, selects 32 bitsout of dbuf [127:0] (19), and outputs them as the head address signal ofinterruption routine jmpadr [31:0] through a signal line 406. Therelationships between intvec 1 [3:0] and the selected bits are 0:dbuf[127:96], 1:dbuf [95:64], 2:dbuf [63:32] and 3:dbuf [31:0].

The stored PC holding register (404) captures the value of spc [31:0](12) by asserting spcupdt (13), and outputs the held value as a targetaddress signal of RTE rtnadr [31:0] through a signal line 407.

The selector 1 (405), to which pftype [1:0] (205) is inputted as aselection signal, selects one out of a 32-bit 0-fixed value, vecadr[31:0] (411), jmpadr [31:0] (406) and rtnadr [31:0] (407), and outputsthe result as a prefetch address signal pfadr [31:0] (30). Thecorresponding relationships between pftype [1:0] and the selected signalare 0:fixed value, 1:vecadr [31:0], 2:jmpadr [31:0] and 3:rtnadr [31:0].In this embodiment, although the 32-bit 0-fixed value is supposed to beselected when pftype [1:0] is 0, the choice is not limited to the 32-bit0-fixed value, but may be any other appropriate value because noprefetch request is made.

Next, the actions of the information processing apparatus of thisembodiment will be described.

FIG. 10 is a timing chart of the actions of the information processingapparatus described so far. The instructions to be executed, the timingof interruption request and the interruption vector are the same asthose respectively described above with reference to FIG. 5.

In cycle 3, the INTC (9) outputs the interruption vector 2 as theinterruption request signal intreq and the interrupt factor signalintvec [8:0], and requests the CPU (1) branch into the interruptionroutine corresponding to the interruption vector 2. In the same cycle,the state of the prefetch request state machine (201) is made transitionto the VECF0 state, and pfreq is asserted. Further, the address of theinterruption vector as the interruption factor 2 is calculated by theaddress calculation unit (202), and address 8 is outputted as pfadr[31:0].

Then in cycle 4, the control unit (3) receives a prefetch request foraddress 8, outputs entry 0 as memadr, asserts memread, and makes arequest to the memory (4) to read entry 0. In the same cycle, itreceives pfack assert from the control unit (3), and the state of theprefetch request state machine (201) is made transition to VECF1.

In cycle 5, the CPU (1) outputs the target address 130 of RTEinstruction as spc [31:0] in order to store it into a memory elementsuch as a built-in RAM, and asserts the signal spcupdt indicating theeffective timing of spc [31:0]. In the same cycle, the addresscalculation unit (202) holds the target address of RTE instruction inthe stored PC holding register (404) for use in prefetching the targetaddress.

Next in cycle 6, the CPU (1) accesses address 8 in order to read theinterruption vector as the accepted interrupt factor 2 from the memory.

Further in the same cycle, the read data of entry 8 prefetched in cycle4 is outputted from the memory (4) as memrd [127:0], and the controlunit (3) asserts dbupdt to capture memrd [127:0] into the data buffer(7).

Further in the same cycle, in response to the assertion of dbupdt, thestate of the prefetch request state machine (201) is made transition toJMP0.

Next in cycle 7, the interruption vector as the interrupt factor 2 isread out. Since the interruption vector was prefetched in advance incycles 3 through 6, no suspension of access due to the latency of memoryaccess occurs.

Further in the same cycle, the state of the prefetch request statemachine (201) is made transition to JMP1, and pfreq is asserted.Further, the address calculation unit (202) selects the head address ofthe interruption routine of the interruption factor 2 out of dbuf[127:0] in which the interruption vector is stored, and outputs address512 as pfadr [31:0].

Then in cycle 8, access to the head address of the interruption routine512 of the interruption factor 2 is started. Further in the same cycle,the control unit (3) receives a prefetch request for the address 512,outputs entry 32 as memadr, asserts memread, and gives a request to readentry 32 to the memory (4).

Further in the same cycle, in response to assertion of pfack from thecontrol unit (3), the state of the prefetch request state machine (201)is made transition to IDLE.

Next in cycle 10, the van instruction of the interruption routine of theinterruption factor 2 is read out. Since the van instruction wasprefetched in advance in cycles 7 through 10, the suspension of accessdue to the latency of memory access is limited to one cycle.

Although in this embodiment, the van instruction of the interruptionroutine of the interruption factor 2 is prefetched from cycle 7 onward,it is also possible to start prefetching in cycle 6 by configuringprefetch address calculation unit (2) so as to select the address of thevan instruction of the interruption routine out of memrd [127:0] inwhich the interruption vector is stored. In that case, no suspension ofaccess due to the latency of memory access occurs.

Next in cycle n-2, entry 50 is first hit, and the control unit assertsibupdt in order to store entry 50 into the instruction buffer (8).

Then in cycle n-1, an RTE instruction is decoded from ibuf [127:0] inprefetch address calculation unit (2), the state of the prefetch requeststate machine (201) is made transition to RIN, and pfreq is asserted.Further, the target address of RTE held by the stored PC holdingregister (404) in cycle 5 is selected in the address calculation unit(202) , and the address 132 is outputted as pfadr [31:0].

Next in cycle n, the control unit (3) outputs entry 8 as memadr inresponse to a prefetch request for the address 132, asserts memread, andgives a request to read entry 8 to the memory (4). IN the same cycle, inresponse to assertion of pfack from the control unit (3), the state ofthe prefetch request state machine (201) is made transition to IDLE.

Then in cycle n+4, the instruction of the target address of RTE isaccessed and, in the following cycle n+5 the instruction of the targetaddress is read out. Since the instruction of the target address wasprefetched in advance in cycles n-1 through n+2, no suspension of accessdue to the latency of memory access occurs.

Although in this embodiment, prefetch address calculation unit (2)prefetches the target address of RTE by decoding the RTE instruction,the target address may as well be prefetched by decoding all theinstructions branching into stored target address, including the targetinstruction (address) of return from a subroutine(RTS).

As hitherto described, this embodiment of the invention can provide aninformation processing technique permitting effective prefetch, ensuringhigh performance and meeting a high-level requirement for real timeperformance even with an application involving many interruptions.

Embodiment 2

Embodiment 2 of the invention will be described with reference to FIG.11 through FIG. 21.

FIG. 11 shows an overall configuration of an information processingapparatus, which is Embodiment 2 of the invention.

The information processing apparatus of this embodiment comprises a CPU(1), a memory (4), a cache (5), a selector 0 (6), a selector 1 (10), aprefetch address calculation unit (1101), a return from subroutine (RTS)instruction buffer (1102), an instruction buffer (1103) and a controlunit (1111).

As the functions of the CPU (1), the memory (4), the cache (5), theselector 0 (6) and the selector 1 (10) are the same as those of theirrespective counterparts of Embodiment 1 described above with referenceto FIG. 1, their description is omitted here.

The prefetch address calculation unit (1101), when a series ofinstructions are stored into the instruction buffer (1103), detects aseries of instructions for branch out of the stored series ofinstructions, calculates the address to be accessed next in accordancewith those instructions, and generates a request to read the series ofinstructions containing the instruction of the address out of the memory(4). An example of the series of instructions for branch will bedescribed later with reference to FIG. 15.

For the prefetch so far described, the prefetch address calculation unit(1101) outputs to the control unit (1111) a prefetch address signalpfadr [31:0] indicating the address of the prefetch instruction on thesignal line 30 and a prefetch request signal pfreq indicating theoccurrence of a prefetch request on the signal line 29.

The prefetch address calculation unit (1101) further receives aninstruction buffer output signal ibuf [175:0] from the instructionbuffer (1103) through a signal line 1104, the upper bit valid signalibvh of the instruction buffer through a signal line 1108, and a signalpfack from the control unit (1111) through the signal line 31, for usein the calculation of pfadr [31:0] and pfreq.

Further the prefetch address calculation unit (1101), when a series ofinstructions is stored into the instruction buffer (1103), detects abranch instruction for subroutine out of the stored the series ofinstructions and, in connection with that, asserts update a signalrtsupdt of a return from subroutine (RTS) instruction through a signalline 1105.

The instruction buffer (1103) holds the series of instructions includingthe instruction currently being accessed by the CPU and the series ofinstructions previously accessed by the CPU, and outputs them as theinstruction buffer output signal ibuf [175:0] through a signal line1104. It outputs the validity of the upper bits ibuf [175:128] of ibuf[175:0] as an instruction buffer upper bit valid signal ibvh through asignal line 1108. It further outputs the address of the series ofinstructions held by the instruction buffer (1103) as itag [31:4](signal line 1109).

The instruction buffer (1103) receives through the signal line 28 aninstruction buffer update signal ibufupd indicating the update timing ofthe series of instructions held by the instruction buffer, and capturescacheadr [31:4] and cacherd [127:0].

The RTS (return from subroutine) instruction buffer (1102) stores aplurality of series of instructions including a branch instruction forbranch. It receives cacheadr [31:4] and cacheread, performs hitdetermination of the plurality of stored series of instructionsregarding the reading of the cache (5) indicated by those signals. Whena hit is determined, it will assert RTS instruction buffer hit signalrtshit through a signal line 1106, and outputs the hit series ofinstructions as a RTS buffer read data rtsbufrd [127:0] through a signalline 1107.

The RTS instruction buffer (1102) receives through the signal line 1105the RTS buffer instruction update signal rtsbupdt indicating the updatetiming of a series of instructions held by the RTS instruction buffer,and captures itag [31:4] and ibuf [127:0].

The control unit (1111) performs control pertaining to transfers ofinstructions and data between the CPU (1) and the memory (4) byinputting/outputting control signals to and from the memory (4), the CPU(1), the prefetch address calculation unit (1101), the cache (5), theselector 0 (6), the selector 1 (10), the instruction buffer (1103) andthe RTS instruction buffer (1102).

More specifically, as will be described later, it controls processing inthose sections by asserting the necessary ones of various controlsignals which are inputted at prescribed timings.

Next, details of the elements of the configuration will be described.

FIG. 12 shows a detailed configuration of the instruction buffer (1103).

The instruction buffer (1103) comprises a flip-flop (1220), a currentinstruction tag (1203), a current instruction buffer (1201), a previousinstruction tag(1204), a previous instruction buffer (1202), an adder(1205), a comparator (1208), a driver (1221), a driver (1206) and adriver (1207).

The flip-flop (1220), to which cacheadr [31:4] (24) is inputted, outputsthe input value as cacheadr 1 [31:4] through a signal line 1214 afterone cycle.

The current instruction tag (1203) holds the address of the series ofinstructions stored in the current instruction buffer (1201). Inresponse to the assertion of ibupdt (28), it captures the value ofcacheadr 1 [31:4] (1214), and outputs the held value as itag 0 [31:4]through a signal line 1210.

The current instruction buffer (1201), in response to the assertion ofibupdt (28), captures the value of cacherd [127:0] (20), and outputs theheld value as ibuf0 [127:0] through a signal line 1211.

The previous instruction tag (1204) holds the address of the series ofinstructions stored in the previous instruction buffer (1202). Inresponse to the assertion of ibupdt (28) , it captures the value of itag0 [31:4] (1210), and outputs the held value as itag 1 [31:4] through asignal line 1212.

The previous instruction buffer (1202) captures ibuf0 [47:0] out ofibuf0 [127:0] (1211) in response to assertion of ibupdt (28), andoutputs the held value as ibuf1 [47:0] through a signal line 1213.

The adder (1205) output the result of adding 1 to itag 1 [31:4] (1212)as itag 2 [31:4] through a signal line 1214.

The comparator (1208) compares itag 0 [31:4] (1210) with itag 2 [31:4](1214) and, when they are found identical, asserts the instructionbuffer upper bit valid signal ibvh through the signal line 1108.Asserting ibvh (1108) means consecutiveness of the series ofinstructions stored in the current instruction buffer (1201) and theseries of instructions stored in the previous instruction buffer (1202).

The driver (1221) takes in itag 0 [31:4] (1210), and outputs theinputted value as itag [31:4] (signal line 1109).

The driver (1206) and the driver (1207), to which ibuf0 [127:0] (1211)and ibuf1 [47:0] (1213) are respectively inputted, output the inputvalues respectively as ibuf [127:0] out of ibuf [175:0] (1104) and asibuf [175:128] out of ibuf [175:0] (1104). When asserting ibvh (1108),ibuf [175:0] (1104) outputs 11 consecutive instructions.

FIG. 13 shows a detailed configuration of the RTS instruction buffer(1102).

The RTS instruction buffer (1102) comprises an AND gate (1305), an RTStag 0 (1300), a validity bit 0 (1301), a hit bit 0 (1302) , an RTSbuffer 0 (1303), a comparator 0 (1304), an AND gate (1325), an RTS tag 1(1320), a validity bit 1 (1321) , a hit bit 1 (1322), an RTS buffer 1(1323), a comparator 1 (1324), an OR gate (1340), an AND gate (1343), aselector (1341), a flip-flop (1344) and an RTS update pointercalculation circuit (1342).

In this embodiment of the invention, the RTS instruction buffer (1102)holds two entries at the maximum in the RTS buffer 0 (1303) and the RTSbuffer 1 (1323).

The AND gate (1305) outputs the “and” of a RTS instruction buffer updatesignal rtsbupdt (1105) and rtspnt [0] as an RTS buffer 0 update signalrstupdt0 (signal line 1314). rtspnt [0] is bit 0 of an RTS updatepointer signal rtspnt [1:0] (signal line 1352) indicating the RTS bufferto be updated.

The RTS tag 0 (1300) holds the addresses of series of instructions to bestored in the RTS buffer 0 (1303). It captures the value of itag [31:4](1109) in response to the assertion of rstupdt0 (1314), and outputs theheld value as rtstag0 [31:4] (signal line 1310).

The validity bit 0 (1301) stores the validity or invalidity of anyseries of instructions stored in the RTS buffer 0 (1303) (1: valid, 0:invalid), and outputs the stored value as v0 through a signal line 1311.The validity bit 0 (1301) has an initial value of 0, and is set to 1 inresponse to the assertion of rstupdt0 (1314).

The RTS buffer 0 (1303) captures the value of ibuf [127:0] (1104) inresponse to the assertion of rstupdt0 (1314), and outputs the held valueas rtsbuf0 [127:0] through a signal line 1315.

The comparator 0 (1304), to which cacheadr [31:4] (24), rtstag0 [31:4](1310) and v0 (1311) are inputted, asserts an RTS buffer 0 hit signalrtshit0 through a signal line 1313 when cacheadr [31:4] (24) and rtstag0[31:4] (1310) are identical and v0 (1311) is 1. Asserting rtshit0 meansthat an RTS buffer 0 (1301) stores the series of instructions of theaddress indicated by cacheadr [31:4] (24) and the RTS buffer 0 (1303)can output the series of instructions (RTS buffer 0 hit).

The hit bit 0 (1302) stores information indicating whether or not anyseries of instructions stored in the RTS buffer 0 (1303) is hit (1: hit,0: not hit), and outputs the stored value as hit0 (signal line 1312).The hit bit 0 (1302) has an initial value of 0. It is set in response tothe assertion of rsthit0 (1313) and reset in response to the assertionof rstupdt0 (1314).

The AND gate (1325) outputs the “and” of the RTS instruction bufferupdate signal rtsbupdt (1105) and rtspnt [1] as an RTS buffer 1 updatesignal rstupdt1 through a signal line 1334.

The RTS tag 1 (1320) holds the addresses of series of instructions to bestored in the RTS buffer 1 (1323). In response to the assertion ofrstupdt1 (1334), it captures the value of itag [31:4] (1109), andoutputs the held value as rtstag1 [31:4] through a signal line 1330.

The validity bit 1 (1321) stores the validity or invalidity of anyseries of instructions stored in the RTS buffer 1 (1323) (1: valid, 0:invalid), and outputs the stored value as v1 through a signal line 1331.The validity bit 1 (1321) has an initial value of 0, and is set to 1 inresponse to the assertion of rstupdt1 (1334).

The RTS buffer 1 (1323) captures the value of ibuf [127:0] (1104) inresponse to the assertion of rstupdt1 (1334), and outputs the held valueas rtsbuf1 [127:0] through a signal line 1335.

The comparator 1 (1324), to which cacheadr [31:4] (24), rtstag1 [31:4](1330) and v1 (1331) are inputted, asserts an RTS buffer 1hit signalrtshit1 through a signal line 1333 when cacheadr [31:4] (24) and rtstag1[31:4] (1330) are identical and v1 (1331) is 1. Asserting rtshit1 meansthat the RTS buffer 1 (1323) stores the series of instructions of theaddress indicated by cacheadr [31:4] (24) and the RTS buffer 1 (1323)can output that series of instructions (RTS buffer 1 hit).

The hit bit 1 (1322) stores information indicating whether or not anyseries of instructions stored in the RTS buffer 1 (1323) is hit (1: hit,0: not hit), and outputs the stored value as hit1 (signal line 1332).The hit bit 1 (1332) has an initial value of 0. It is set in response tothe assertion of rsthit1 (1333) and reset in response to the assertionof rstupdt1 (1334).

The OR gate (1340) outputs the “or” of rtshit0 (1313) and rtshit1 (1333)as rtshitor (signal line 1350).

The AND gate (1343) outputs the “and” of rtshitor (1351) and cacheread(25) as the RTS instruction buffer hit signal rtshit through a signalline 1106.

Assertion of rtshit (1106) means that read data can be taken out of theRTS buffer 0 (1303) or the RTS buffer 1 (1323) in compliance with arequest for reading the cache indicated by the assertion of cacheread(25) out of the entry of cacheadr [31:4] (24).

The selector (1341), to which rtshit0 (1313) and rtshit1 (1333) areinputted as selection signals, selects one out of rtsbuf0 [127:0] (1315)and rtsbuf1 [127:0] (1335), and outputs the selected one as rtsbufslctdthrough a signal line 1351. The relationships between the value ofrtshit0 (1313) or rtshit1 (1333) and the selected signal are:

{rtshit0, rtshit1}=10:rtsbuf0 [127:0]

{rtshit0, rtshit1}=01:rtsbuf1 [127:0]

Thus, the selector (1341) selects the output of the hit RTS buffer outof the RTS buffer 0 and the RTS buffer 1.

The flip-flop (1344), to which rtsbufslctd (1351) is inputted, outputsone cycle afterwards the input value as RTS instruction buffer read datartsbufrd [127:0] through a signal line 1107.

The RTS update pointer calculation circuit (1342), to which hit1 (1332),hit0 (1312), v1 (1331) and v0 (1311) are inputted, provides its outputas the RTS update pointer signal rtspnt [1:0] indicating the RTS bufferto be updated through a signal line 1352.

Meanings corresponding to the value of the RTS update pointer signalrtspnt [1:0] (1352) are as follows.

01: Update the RTS buffer 0

10: Update the RTS buffer 1

The relationships between the inputs hit1 (1332), hit° (1312), v1 (1331)and v0 (1311) of the RTS update pointer calculation circuit (1342) andits output rtspnt [1:0] (1352) are as follows.

{hit1, hit0, v1, v0}=1???→rtspnt [1:0]=10

{hit1, hit0, v1, v0}=01??→rtspnt [1:0]=01

{hit1, hit0, v1, v0}=000?→rtspnt [1:0]=10

{hit1, hit0, v1, v0}=0000 rtspnt [1:0]=01

Default→rtspnt [1:0]=00

“?” means “don't care”. Thus, the buffer to be updated is selected in analgorithm in which hit buffers are searched first and, in the absence ofany hit buffer, then invalid buffers are searched.

Before describing prefetch address calculation unit (1101) in detailwith reference to FIG. 14, the series of instructions for branch to bedecoded by prefetch address calculation unit (1101) will be describedwith reference to FIG. 15.

FIG. 15 illustrates a series of instructions for branch consisting ofthree instructions such as No. 1 through No. 3, supposed for thisembodiment of the invention. Since instruction No. 1 is a 32-bitinstruction, it is equivalent to four 16-bit instructions.

The instruction coded “MOVIS20 #imm20, Rn” listed as No. 1 is aninstruction to shift a 20-bit immediate value (bits 23 through 16 and 11through 0 in the instruction code) by eight bits and store the shiftedvalue into a register Rn. n in Rn is the register number, represented bybits 26 through 23 in the instruction code. The number of registers tobe equipped by the CPU supposed for this embodiment is 16, and theregister numbers n ranges from 0 to 15.

The instruction coded “ADD #imm8, Rn” listed as No. 2 is an instructionto add the immediate value of eight bits (bits 7 through 0 in theinstruction code) and values to be stored in the register Rn and storethe results in Rn.

The instruction coded “JSR @Rn” listed as No. 3 is an branch instructionto a subroutine, and the target address for branch is a value stored inthe register Rn.

Where a series of instructions is found matching the order ofinstructions No. 1 through No. 3 and identical in the register number ofeach instruction, a subroutine branch to any desired address in a 28-bitrange is executed. A series of instructions for branch satisfying theseconditions is defined as a “valid series of instructions for branch”.

FIG. 14 shows a detailed configuration of the prefetch addresscalculation unit (1101).

The prefetch address calculation unit (1101) comprises an instructionpre-decoder 0 (1400), an instruction pre-decoder 1 (1401), . . . , aninstruction pre-decoder 7 (1407), an OR gate (1431), a priority encoder(1410), a selector (1411), an instructions sequence circuit (1412), aregister number identity determining circuit (1413), a prefetch requestcalculation circuit (1415), an immediate value extracting circuit(1414), an adder (1416), an OR gate (1433) and a leading edge detectingcircuit (1418).

Each of the 16-bit segments into which ibuf [127:0] is divided, isinputted to each of the instruction pre-decoder 0 (1400), theinstruction pre-decoder 1 (1401), . . . , the instruction pre-decoder 7(1407).

The instruction of the head address in the series of instructions of theentry outputted by ibuf [127:0] is inputted to the instructionpre-decoder 0 (1400). When the inputted instruction is a JSRinstruction, the instruction pre-decoder 0 (1400) asserts jsr [0] out ofjsr [7:0] through a signal line 1420.

Similarly, the instruction pre-decoder 1 (1401) decodes the secondinstruction in the series of instructions of the entry outputted by ibuf[127:0], and outputs the result as jsr [1].

The types of the third, fourth, . . . , sixth instructions or data arealso decoded.

Similarly, the instruction pre-decoder 7 (1407) decodes the eighthinstruction in the series of instructions of the entry outputted by ibuf[127:0], and outputs the result as jsr [7].

The OR gate (1431) calculates the “or” of the bits of jsr [7:0], andoutputs the result as jsror 70 through a signal line 1430. Theconfiguration hitherto described causes, when there is at least one JSRinstruction in the series of instructions of the entry outputted by ibuf[127:0], jsror 70 to be asserted.

The OR gate (1433) calculates the “or” of the bits of jsr [7:1], andoutputs the result as jsror 71 through a signal line 1432.

The leading edge detecting circuit (1418) detects the leading edge ofjsror 71 (1432), and asserts during one cycle the RTS buffer updatesignal rtsbupdt (1105) at the same timing as the detection of theleading edge.

In the configuration described above, when there is at least one JSRinstruction in the seventh instructions from the van of the series ofinstructions in the entry outputted by ibuf [127:0], the RTS bufferupdate signal rtsbupdt (1105) will be asserted to store the series ofinstructions containing the target address of RTS instruction into theRTS instruction buffer to prepare for a return from the subroutine. Whenthe final instruction of the series of instructions in the entryoutputted by ibuf [127:0] is a JSR instruction, since that series ofinstructions contains no target instruction of RTS, storing inpreparation for return will be meaningless. For this reason, when thereis any JSR instruction among the seventh instructions from the head ofthe series of instructions in the entry outputted by ibuf [127:0],rtsbupdt (1105) will be asserted.

The priority encoder (1410) outputs the result of encoding jsr [7:0](1420) as inst_sel [2:0] through a signal line 1421. The relationshipsbetween the inputs and outputs of the priority encoder (1410) are asfollows.

10000000→000

?1000000→001

??100000→010

???10000→011

????1000→100

?????100→101

??????10→110

???????1→111

Default 000

“?” means “don't care”.

The selector (1411) , to which inst_sel [2:0] (1421) is inputted as theselection signal, outputs the result of selecting 64 bits out of ibuf[175:0] as ibuf_slctd [63:0] through a signal line 1422 . Therelationships between the values of inst_sel [2:0] (1421) and the bitsof selected ibuf [175:0] are as follows.

inst_sel [2:0]=000: ibuf [63:0]

inst_sel [2:0]=001: ibuf [79:16]

inst_sel [2:0]=010: ibuf [95:32]

inst_sel [2:0]=011: ibuf [111:48]

inst_sel [2:0]=100: ibuf [127:64]

inst_sel [2:0]=101: ibuf [143:80]

inst_sel [2:0]=110: ibuf [159:96]

inst_sel [2:0]=111: ibuf [175:112]

In the above-described configuration comprising the instructionpre-decoder 0 (1400), the instruction pre-decoder 1 (1401) , . . . , theinstruction pre-decoder 7 (1407), the priority encoder (1410) and theselector (1411), four consecutive instructions ending with a JSRinstruction are selected out of the series of instructions stored inibuf [175:0], and outputted as ibuf slctd [63:0] (1422). Further, in thepresence of a plurality of JSR instructions in ibuf [175:0], fourconsecutive instructions including a JSR instruction nearer the top areselected.

The instruction sequence determining circuit (1412) checks whether ornot the series of instructions outputted as ibuf slctd [63:0] (1422) isin the order of instructions in the series of instructions for branchdescribed with reference to FIG. 15 and, when it does, asserts order hitthrough a signal line 1423.

The register number identity determining circuit (1413), supposing theorder of instructions in the series of instructions for branch describedwith reference to FIG. 15 from the series of instructions outputted asibuf slctd [63:0] (1422), extracts each register number of the threeinstructions and, when all the register numbers are found identical,asserts index_hit through a signal line 1424.

The immediate value extracting circuit (1414), supposing the order ofinstructions in the series of instructions for branch described withreference to FIG. 15 from the series of instructions outputted as ibufslctd [63:0] (1422), extracts the immediate value of “MOVIS20 #imm20,Rn”. Then it performs leftward shifting by eight bits and extension ofthe upper bit 0, and outputs the result as imm0 [31:0] through a signalline 1425. Similarly, after extracting the immediate value of “ADD#imm8, Rn”, it performs extension of the upper bit 0, and outputs theresult as imm1 [31:0] through a signal line 1426.

The adder (1416) adds imm0 [31:0] (1425) and imm1 [31:0] (1426), andoutputs the result as the prefetch address signal pfadr [31:0] (signalline 30) indicating the address of the prefetch instruction.

The prefetch request calculation circuit (1415), to which are inputtedpfack (31) indicating the acceptance of a prefetch request, theinstruction buffer upper bit valid signal ibvh (1108), jsror 70 (1430),inst_sel [2:0] (1421), order_hit (1423) and index_hit (1424), asserts ornegates the prefetch request signal pfreq (29). The conditions ofassertion and negation of pfreq (29) are as follows.

The conditions of assertion are:

{ibvh, inst_sel [2:0], jsror 70, order_hit,index_hit}=1_(—)111_(—)1_(—)1_(—)1   (1)

{ibvh, inst_sel [2:0], jsror 70, order_hit,index_hit}=1_(—)110_(—)1_(—)1_(—)1   (2)

{ibvh, inst_sel [2:0], jsror 70, order_hit,index_hit}=1_(—)101_(—)1_(—)1_(—)1   (3)

{ibvh, inst_sel [2:0], jsror 70, order_hit,index_hit}=?_(—)100_(—)1_(—)1_(—)1   (4)

{ibvh, inst_sel [2:0], jsror 70, order_hit,index_hit}=?_(—)011_(—)1_(—)1_(—)1)   (5)

{ibvh, inst_sel [2:0], jsror 70, order_hit,index_hit}=?_(—)010_(—)1_(—)1_(—)1   (6)

{ibvh, inst sel [2:0], jsror 70, order_hit,index_hit}=?_(—)001_(—)1_(—)1_(—)1   (7)

{ibvh, inst sel [2:0], jsror 70, order hit, indexhit}=?_(—)000_(—)1_(—)1_(—)1   (8)

The condition of negation is:

pfack=1

To add, “?” means “don't care”. Conditions of assertion (1) through (3)are intended to restrain erroneous prefetch requests, where part of aseries of instructions for branch is included in ibuf [175:127], byconditioning assertion on the inclusion of 1 in the instruction bufferupper-order bit valid signal ibvh (1108) , namely the inclusion of 11consecutive instructions in ibuf [175:0].

In the configuration described above, the prefetch address calculationunit (1101) detects a valid series of instructions for branch out ofseries of instructions outputted as ibuf [175:0], and outputs a prefetchrequest of the target address for branch to the control unit (1111).

Next, the operations of the information processing apparatus of thisembodiment will be described.

FIG. 16 is a timing chart of the actions of the information processingapparatus of this embodiment of the invention. FIG. 17 illustrates anexample of program arrangement on the memory. A valid series ofinstructions for branch exists in entry 8, and a return from subroutineinstruction (RTS instruction) exists in entry 100. The timing chart ofFIG. 16 refers to the operations of the information processing apparatusexecuting the program shown in FIG. 17.

In cycle 1, entry 8 is first hit, and in the following cycle 2 thecontrol unit (1111) asserts ibufupdt to store entry 8 into theinstruction buffer (1103).

Then in cycle 3, prefetch address calculation unit (1101) detects avalid series of instructions for branch existing in entry 8 from ibuf[127:0], asserts pfreq, and output a prefetch address 1008 as fpadr[31:0]. In the same cycle, it asserts an rtsbupdt signal to store theentry including the branching instruction currently being hit into theRTS instruction buffer with a view to prepare for a return from thesubroutine. By storing here the entry including the branchinginstruction currently being hit into the RTS instruction buffer, aseries of instructions can be read out of the RTS instruction buffereven when the cache is updated by the execution of a subroutine and noentry of the target address of return exists in the cache.

Next in cycle 4, the control unit (1111), by receiving a prefetchrequest for address 1008, outputs entry 63 as memadr, asserts memaread,and gives a request to read entry 63 to the memory (4). In the samecycle, in response to assertion of pfack from the control unit (3),pfreq is negated. Further in the same cycle, in response to rtsbupdt,entry 0 is stored into RTS tag 1 in the RTS instruction buffer, and theseries of instructions of entry 0, into the RTS buffer 1.

Then in cycle 6, the read data of entry 63 prefetched in cycle 4 areoutputted from the memory (4) as memrd [127:0] and, though no signal ismentioned, the control unit (1111) outputs a control signal for storingmemrd [127:0] into the cache, and entry 63 is stored into the cache inthe next cycle.

Next in cycle 7, though the target address (branch destination) 1008 ofan instruction to branch into a subroutine existing in entry 8 isaccessed, no penalty due to a cache error occurs because address 1008was prefetched in cycle 4.

It is supposed that the program of the subroutine continues to beexecuted, the subroutine is registered in the cache by the time cycle ncomes, and entry 8 no longer exists in the cache.

Next in cycle n+2, though an RTS instruction existing in entry 100 isexecuted, and address 138 is accessed, no penalty due to a cache erroroccurs because the entry of the target address of RTS was stored intothe RTS buffer 1 in cycle 4 and the RTS buffer 1 is hit.

FIG. 18 is a timing chart of the actions of prefetch address calculationunit (1101) in a case in which there is a valid series of instructionsfor branch spanning two entries. FIG. 19 illustrates an example ofprogram arrangement in a case in which there is a valid series ofinstructions for branch spanning entry 8 and entry 9. The timing chartof FIG. 18 refers to the operations of prefetch address calculation unit(1101) executing the program shown in FIG. 19.

In cycle 1, entry 8 is first hit and, following it, the control unit(1111) asserts ibufupdt in the next cycle 2 to store entry 8 into theinstruction buffer (1103).

Next, in response to the assertion of ibufupdt, entry 8 is stored intothe current instruction tag and the series of instructions of entry 8 isstored into the current instruction buffer in cycle 3.

As the program proceeds, entry 9 is first hit in cycle 7, and in thefollowing cycle 8, the control unit (1111) asserts ibufupdt to storeentry 9 into the instruction buffer (1103).

Then, in response to the assertion of ibufupdt, entry 9 is stored intothe current instruction tag and the series of instructions of entry 9 isstored into the current instruction buffer in cycle 10. In the samecycle, entry 8 is stored into the previous instruction tag and theseries of instructions of entry 8 is stored into the previousinstruction buffer. As a result of storing of consecutive entries intothe buffer 0 and the buffer 1, 11 consecutive instructions are outputtedas ibuf [175:0], and ibvh is asserted. Then, prefetch addresscalculation unit (1101) detects a series of instructions for branchspanning entry 8 and entry 9 from ibuf [175:0], asserts pfreq, andoutputs the prefetch address 1008 as fpadr [31:0]

As hitherto described, the prefetch address calculation unit (1101) candecode a valid series of instructions for branch spanning two entriesand execute the prefetch request.

FIG. 20 illustrates an example of program flow, and will be used laterfor explaining FIG. 21. The program shown in FIG. 20 is executed in thesequence of main routine subroutine 1→subroutine 2→subroutine1→subroutine 3→subroutine 1→main routine.

The end points of straight lines shown in FIG. 20 respectively representthe starting point of the main routine, a branch instruction to asubroutine, an instruction of return from the subroutine, a targetinstruction for return from the subroutine and the end of the mainroutine. In the vicinities of some of the end points, correspondingaddresses (entries) for use in the explanation of FIG. 21 are stated.

FIG. 21 is a timing chart of the actions to update the RTS instructionbuffer in the program flow illustrated in FIG. 20.

First, the main routine stats in cycle 1. As the main routine proceeds,an instruction of branching into subroutine 1 is detected in cycle m-2,and the RTS buffer update signal rtsbupdt is asserted. Since the RTSupdate pointer here is “10”, the series of instructions of entry 6 isstored into the RTS buffer 1 in cycle m-1. In the same cycle, 1 is setas the validity bit 1, and the value of the RTS pointer becomes “01”.

Next, subroutine 1 starts in cycle m. As subroutine 1 proceeds, aninstruction of branching into subroutine 2 is detected in cycle n-2, andthe RTS buffer update signal rtsbupdt is asserted. Since the RTS updatepointer here is “01”, the series of instructions of entry 105 is storedinto the RTS buffer 0 in cycle n-1. In the same cycle, 1 is set as thevalidity bit 0, and the value of the RTS pointer becomes “10”.

Next, subroutine 2 is started in cycle n. As subroutine 2 proceeds, theRTS instruction is executed in cycle o-1.

Next, the program returns to subroutine 1 in cycle o, and the RTS buffer0 is hit in the same cycle, and 1 is set as the hit bit 0, and the valueof the RTS pointer becomes “01” in the following cycle o+1.

As subroutine 1 proceeds, a branch instruction into subroutine 3 isdetected in cycle p-2, and the RTS buffer update signal rtsbupdt isasserted. As the RTS update pointer here is “01”, the series ofinstructions of entry 107 is stored into the RTS buffer 0 in cycle p-1.In the same cycle, 1 is set as the validity bit 0, 0 is set as the hitbit 0, and the value of the RTS pointer becomes “10”.

Next, subroutine 3 starts in cycle p. As subroutine 3 proceeds, the RTSinstruction is executed in cycle q-1.

Then, the program returns to subroutine 1 in cycle q. In the same cycle,the RTS buffer 0 is hit. In the following cycle q+1, 1 is set as the hitbit 0, and the value of the RTS pointer becomes “01”.

Next, the program returns to the main routine in cycle r. In the samecycle, the RTS buffer 1 is hit. In the following cycle r+1, 1 is set asthe hit bit 1, and the value of the RTS pointer becomes “10”.

The RTS updating algorithm described above can achieve such efficientupdating matching the characteristic of the RTS buffer that everyupdated RTS buffer is hit, and no hit RTS buffer is reused.

As hitherto described, this embodiment can provide a high-performanceinformation processing technique permitting at low cost updating of aninstruction buffer ready for effective prefetch to branch instructionsand returning to the subroutine with a small volume of hardware.

While the present invention has been described with reference topreferred embodiments thereof, the invention is not limited to theseembodiments, but the design can obviously be modified in various wayswithout dethroughting from the true spirit and scope of the invention.

The information processing apparatus according to the invention,provided with a CPU, a memory and prefetch means, can be effectivelyapplied to a technique for prefetch to an interruption routine and atarget instruction for return from interrupt. It can also be effectivelyapplied to prefeching to the target information for branch of asubroutine and the storing the target information of RTS, withparticular effectiveness to high-performance information processingapparatuses.

1. An information processing apparatus comprising: a memory that storesa plurality of instructions each having m bits; a first bus connected tothe memory and having a bus width of 128 bits as m bits×n, where n is aninteger; a cache connected to the first bus to store instructionsselected from the plurality of instructions in the memory; a second busconnected to the cache and having a bus width of 128 bits as m bits×n; aselector connected to the first bus and the second bus; a third busconnected to the selector and having a bus width of 32 bits comprising mbits×L, where L is defined by L<n; and a CPU being connected to thethird bus.
 2. The information processing apparatus according to claim 1,wherein L=2.
 3. The information processing apparatus according to claim1, wherein an access latency of the memory is
 2. 4. The informationprocessing apparatus according to claim 1, further comprising: aninstruction buffer connected to the second bus; and an addresscalculation unit connected to the instruction buffer, wherein theaddress calculation unit is configured to check whether a branchinstruction and an instruction for calculation of branch target addressexists in the instructions stored in the instruction buffer, and todecode the branch instruction and the instruction for calculation of abranch target address upon existence of them before the CPU executes thebranch instruction and the instruction for calculation of branch target,so the address calculation unit is further configured to calculate thebranch target address and generate a prefetch request to prefetch aninstruction of the branch target address from the memory and store theprefetched instruction into the cache.
 5. The information processingapparatus according to claim 4, upon simultaneous occurrence of theprefetch request from the prefetch address calculation unit and a readrequest from the CPU, priority is given to the read request from theCPU.